The present disclosure relates generally to memory devices and, more particularly, to synchronous memory devices and techniques for controlling data strobe signals during read operations.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present techniques, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Generally, a computing system may include an electronic device that, in operation, communicates information via electrical signals. For example, a computing system may include a processor communicatively coupled to a memory device, such as a dynamic random-access memory (DRAM). In this manner, the processor may communicate with the memory device, to retrieve executable instructions, retrieve data to be processed by the processor, and/or store data output from the processor, using command and/or address signals (CA signals), for instance. These CA signals may be supplied to a common bonding pad, a pin, an external terminal, or the like.
In synchronous memory devices, such as synchronous DRAM (SDRAM), CA signals are provided to the memory device, synchronously, with an external clock signal that may be provided by a processor. Various internal clock signals are generated within the memory device from the external clock signal and are used to synchronize command and data signals to ensure proper operation of the memory device. That is, various internal clock signals are generated and used within the memory device to complete various operations within the memory device, such as read commands and write commands, based on various CA signals. For read commands, some internal circuits and internal clock signals may not be needed in certain modes of operation. For instance, internal data strobe signals that may otherwise be generated and utilized, may not always be needed during all modes of operation. In these instances, power consumption may be unnecessarily increased if the internal clock signals are generated but unused. Embodiments of the present disclosure may be directed to techniques for controlling data strobe signals during read operations, to reduce power consumption during certain modes of operation.